Description
The undergraduate-level course explores the design of combinational or sequential logical circuit. The course starts with understanding the basic concept of logic circuit, the theory of Boolean algebra and physical implementation techniques of logical circuit. Then, the course explores the design of combinational logic including optimization techniques. Also, the course includes the study of storage logic circuits such as latch, flipflops and registers. Finally, the course explores the design of synchronized or asynchronized sequential logic.
Instructor
Kyungbaek Kim
Office : Engineering Building #6, 715
Tel : +82-62-530-3438
Email : kyungbaekkim@jnu.ac.kr
Office Hours : Wed 11:00 ~ 11:45
Time and Location
Tue, Thur 15:00 ~ 16:15, Engineering Building #6, 102
Main Text
- Fundamentals of digital logic with VHDL design, 3rd edition, Brown and Vranesic
Reference Text
- Fundamentals of Logic Design, 6th edition, C. H. Roth Jr
Grading Policy
- Attendance : 10%
- Homework and Quiz : 30%
- Around four to five times of homeworks.
- Around two to three times of pop-up quiz.
- Midterm Exam : 30%
- Final Exam : 30%
Lecture Notes
- 0.Syllabus
- 1.Design Concept
- 2.Introduction to Logic Circuits
- 3.Optimized Implementation of Logic Functions
- 4.Number Representation and Arithmetic Circuits
- 5.Combinational Circuit Building Blocks
- 6.Flip-flops Registers Counters and a Simple Processor
- 7.Synchronous Sequential Circuits
Lecture notes are accessible through the eClass of JNU portal.
Homeworks and Exercises
- Homework 01
- Exercise 01
- Homework 02
- Exercise 02
- Homework 03
- Homework 04
- Homework 05